Integrated circuits are commonly used to make a wide variety of electronic devices, such as memory chips. There is a strong desire to reduce the size of integrated circuits, as well as to increase the density of individual semiconductor components and consequently enhance the functionality of an electronic device. In an effort to increase the density and functionality of a semiconductor component, attempts have been made to create three-dimensional integrated circuits (3D-ICs). Generally, 3D-ICs allow the integration of chips with different functions (e.g., processor, logic, ASIC, memory), offer low manufacturing costs, provide mechanically stable structures, and reduce circuit RC delay and power consumption.
Generally, 3D-ICs include a plurality of semiconductor dies stacked upon one another. In a typical 3D-IC formation process, a plurality of diced, known good dies are selected and bonded to corresponding dies formed on a wafer. Each of the plurality of diced dies and each of corresponding dies formed on the wafer is electrically connected through one or more through-silicon vias (TSV). The resulting stacked die could provide multiple functions or increased density for a single type of function. After the dies in a stack are physically and electrically connected, the stack is encapsulated by placing a molding compound over the plurality of diced dies and the top surface of the wafer. However, conventional technology does not allow the whole area of the top surface of the wafer to be covered with the molding component. Uncovered portions of the wafer are more likely to crack during wafer handling or a die-sawing process because the uncovered portions, which are typically along the edge of the wafer, are not mechanically supported by the molding compound.
Accordingly, there is a need for an improved method to create a stacked die configuration that avoids wafer edge cracking during a die saw process or wafer handling with improved robustness.